Nanowire NMOS Logic Inverter Characterization

Naif, Yasir Hashim (2016) Nanowire NMOS Logic Inverter Characterization. Journal of Nanoscience and Nanotechnology, 16 (6). pp. 5923-5928. ISSN 1533-4880 (Print); 1533-4899 (Online). (Published)

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This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Faculty/Division: Faculty of Engineering Technology
Depositing User: Dr. Yasir Hashim Naif
Date Deposited: 03 May 2016 01:56
Last Modified: 22 Aug 2017 06:52
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