Aznilnda, Zainodin and Aida Khairunisa, Ab. Kadir and M. Nasir, Ayob and Ahmad Fariz, Hasan and Amar Faiz, Zainal Abidin and Fazlinashatul Suhaidah, Zahid and Hazriq Izuan, Jafar and Ismail, Mohd Khairuddin (2014) An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm. Coloquium on Robotics, Unmaned Systems And Cybernetics 2014 (CRUSC 2014). pp. 17-21. (Published)
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Abstract
Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | Combinational logic circuit minimization; Computational inteligence; Firefly algorithm; Numbers of gates; Swarm inteligence. |
| Subjects: | T Technology > TS Manufactures |
| Faculty/Division: | Faculty of Manufacturing Engineering |
| Depositing User: | Mrs. Neng Sury Sulaiman |
| Date Deposited: | 17 Dec 2014 02:49 |
| Last Modified: | 28 Feb 2018 03:58 |
| URI: | http://umpir.ump.edu.my/id/eprint/7831 |
| Download Statistic: | View Download Statistics |
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