Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell

Naif, Yasir Hashim (2016) Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell. In: AIP Conference Proceeding: International Conference on Advanced Science, Engineering and Technology (ICASET 2015) , 21-22 December 2015 , Penang, Malaysia. pp. 1-7., 1774 (050020). ISBN 978-0-7354-1432-7

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Abstract

This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both length ratios of nanowires and logic voltage level (Vdd), and increasing of high logic voltage level of the SiNWT based SRAM cell tends to decrease in the optimized nanowires length ratio with decreasing in current and power.

Item Type:	Conference or Workshop Item (Lecture)
Uncontrolled Keywords:	nanowires; SRAM Cell; Nano-scale SiNWT
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Faculty/Division:	Faculty of Engineering Technology
Depositing User:	Dr. Yasir Hashim Naif
Date Deposited:	22 Nov 2016 07:53
Last Modified:	22 Aug 2017 06:51
URI:	http://umpir.ump.edu.my/id/eprint/15319
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